The present invention is in the field of integrated circuit manufacturing and testing. More specifically it relates to methods and apparatus for measuring the capacitance of various structures in semiconductor wafers as they are processed into integrated circuits.
During the manufacture of integrated circuits, it is frequently necessary to measure the thickness of one structure or another that has been fabricated on the semiconductor wafer. For example, it may be necessary to know the thickness of a dielectric material such as silicon dioxide which has been grown on the wafer. The thickness can be measured indirectly by measuring the capacitance of the structure.
It is known that for a parallel plate capacitor, C=.epsilon.A/d, where C is the capacitance, A is the area of the capacitor, d is the distance between the plates, and .epsilon. is the dielectric constant of the material between the plates. As the capacitance, dielectric constant, and area can all be measured quite accurately, the thickness can be easily calculated.
In a typical wafer, capacitors are necessarily formed by the junction capacitances of P-N diodes. Capacitors are also formed whenever two conductors are separated by an insulator. The conductors may be in the substrate, or above it, and they may be fabricated from polysilicon, metal, or other conductive materials. The known method to measure capacitance during integrated circuit manufacture is to fabricate on the wafer a large capacitor having a value in excess of 1 picofarad. A capacitor of this size is necessary because of the various stray capacitances which exist in and on the wafer and which are measured along with the test capacitance. One plate of the capacitor under test is also coupled to at least one large "testing" contact or pad to allow a test probe to access the capacitor. This pad also contributes to the stray capacitances measured along with the capacitance of the test capacitor.
The problems associated with using capacitance to determine the thickness of a given dielectric material or layer are compounded by the fact that the measured capacitance has two separate components: the capacitance due to fringing effects, which is a function of the capacitor's perimeter, and the capacitance due to the thickness of the dialectric material, which is a function of the capacitor's area. To determine the relative contribution of each of these factors to the total capacitance, two separate capacitors are needed to measure the thickness of a dielectric layer. The first capacitor has a large surface area with respect to its perimeter, allowing the fringing effect to be ignored, and the second capacitor has a large perimeter with respect to its surface area, allowing area effects to be ignored. Although solving two equations for two unknowns is computationally simple, the necessity of using two separate capacitors to obtain the thickness of the dielectric material is a significant disadvantage because each capacitor occupies a large area on the integrated circuit. This area cannot be used for other circuit elements.
The problem of needing two separate capacitors for each measurement of the dielectric is further compounded by the fact that the thickness of the oxide layer or dielectric layer between, for example, a polysilicon layer and a first metal layer is not constant, but varies as a function of what is beneath the polysilicon, due to planarization techniques used in integrated circuit fabrication. Consequently, many different points in the oxide layer must be evaluated to obtain accurate measurements of thickness. However, the number of points that can be measured using known techniques is limited by the dual requirement of large area for the capacitors and the need for two capacitors to measure thickness. Because of the diminishing yield with increasing integrated circuit area, it is undesirable to devote such a large area on the semiconductor wafer to test capacitors and their bonding pads.